The present invention relates to a layout of external coupling electrodes related to power and ground systems of a wiring board and semiconductor chips in a semiconductor device in which a plurality of the semiconductor chips are mounted over the wiring board in piles, and to, for example, a technology effective if applied to a data processing device or the like a SiP (System in Package) with a microcomputer chip and its peripheral chips or the like mounted in a package.
A data processing device called SiP has been described in, for example, a Patent Document 1. In the SiP described in the same document, a microcomputer chip is surface-mounted over the surface of a buildup type wiring board formed with bottom surface solder balls, and a synchronous DRAM (Dynamic Random Access Memory) chip is provided over the microcomputer chip. The back surface of the synchronous DRAM chip is fixedly stuck to the surface of the microcomputer chip. Electrode pads exposed to the surface of the synchronous DRAM chip are coupled by wire bonding to prescribed electrodes provided in outer peripheral edges at the surface of the wiring board. Paths coupled by wire bonding are configured as paths of an address, a command, data and a strobe signal used to gain access to the synchronous DRAM chip by the microcomputer chip and are used as power supply paths of power and ground systems.
The quality of signals in the SiP has been described in, for example, a Patent Document 2. In the same document, there has been described a devise for maintaining signal quality over wirings in a wiring board for coupling a plurality of semiconductor chips within the SiP. It has been described in the documents that, for example, power and ground planes are adopted within the wiring board to stabilize power and ground systems, and external power supply terminals and external ground terminals of the wiring board are made adjacent to each other.